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LM49120TLEVAL Datasheet(PDF) 18 Page - Texas Instruments |
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LM49120TLEVAL Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 29 page ![]() START MSB DEVICE ADDRESS LSB ACK SCL SDA STOP MSB REGISTER DATA LSB ACK R/W LM49120, LM49120TLEVAL SNAS431C – JUNE 2008 – REVISED MAY 2013 www.ti.com Figure 46. Example Write Sequence Table 1. Device Address B7 B6 B5 B4 B3 B2 B1 B0 (R/W) Device 1 1 1 1 1 0 0 0 Address Table 2. Control Registers B7 B6 B5 B4 B3 B2 B1 B0 Shutdown Control 0 0 0 OCL/SE HP/BTL SD_I2CVDD Turn_On _Time PWR_On Output Mode Control 0 1 0 0 MC3 MC2 MC1 MC0 Output Gain Control 1 0 0 0 LS_GAIN HP_GAIN2 HP_GAIN1 HP_GAIN0 Mono Input Volume 1 0 1 MG4 MG3 MG2 MG1 MG0 Control Left Input Volume 1 1 0 LG4 LG3 LG2 LG1 LG0 Control Right Input Volume 1 1 1 RG4 RG3 RG2 RG1 RG0 Control Table 3. Shutdown Control Register Bit Name Value Description 0 Single-Ended headphone mode (Capacitively Coupled) B4 OSC/SE 1 Output Capacitor-less (OCL) headphone mode 0 Single-ended stereo headphone output mode B3 HP/BTL 1 Mono, BTL output mode. I2CVDD acts as an active low RESET input. If I 2CV DD drops below 1.1V, 0 the device is reset and the I2C registers are restored to their default B2 SD_I2CVDD state. 1 Normal Operation. I2CVDD voltage does not reset the device 0 Fast turn on time (120ms) B1 TURN_ON_TIME 1 Normal turn on time (130ms) 0 Device Disabled B0 PWR_ON 1 Device Enabled Table 4. Output Mode Control (HP/BTL = 0) Output Mode MC3 MC2 MC1 MC0 LS Output HP R Output HP L Output Number 0 0 0 0 0 SD SD SD 1 0 0 0 1 GM x M Mute Mute 2 0 0 1 0 2 x (GL x L + GR x R) Mute Mute 2 x (GL x L + GR x R) 3 0 0 1 1 Mute Mute + GM x M 4 0 1 0 0 SD GM x M/2 GM x M/2 5 0 1 0 1 GM x M GM x M/2 GM x M/2 6 0 1 1 0 2 x (GL x L + GR x R) GM x M/2 GM x M/2 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM49120 LM49120TLEVAL |
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