LP5523 datasheet(33/61 Pages) TI2

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LP5523

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SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017

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27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL

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The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output.

36 MISC

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This register contains miscellaneous control bits.

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36 — Bit [7] VARIABLE_D_SEL

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Variable D source selection

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1 = variable D source is the LED test ADC output (LED TEST ADC). This allows, for example, program

execution control with analog signal.

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0 = variable D source is the register 3C (VARIABLE).

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36 — Bit [6] EN_AUTO_INCR

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The automatic increment feature of the serial bus address enables a quick memory write of successive

registers within one transmission.

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1 = serial bus address automatic increment is enabled.

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0 = serial bus address automatic increment is disabled.

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36 — Bit [5] POWERSAVE_EN

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1 = power save mode is enabled.

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0 = power save mode is disabled. See Automatic Power-Save Mode for further details.

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36 — Bits [4:3] CP_MODE

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Charge-pump-operation mode

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00 = OFF

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01 = forced to bypass mode (1×)

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10 = forced to 1.5× mode; output voltage is boosted to 4.5 V

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11 = automatic mode selection

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36 — Bit [2] PWM_PS_EN

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Enables PWM power-save operation. Significant power savings can be achieved, for example, during

ramp instruction.

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36 — Bits [1:0] CLK_DET_EN and INT_CLK_EN

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Program execution is clocked with internal 32.7-kHz clock or with an external clock. Clocking is

controlled with bits INT_CLK_EN and CLK_DET_EN in the following way:

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00 = forced external clock (CLK pin).

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01 = forced internal clock.

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10 = automatic selection.

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11 = internal clock.

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External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be

32.7 kHz for correct operation. If a higher or a lower frequency is used, it affects the program execution

engine operation speed. The detector block does not limit the maximum frequency. External clock

status can be checked with read only bit EXT_CLK_USED in register address 3A, when the external

clock detection is enabled (Bit [1] CLK_DET_EN = high).

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If external clock is not used in the application, CLK pin should be connected to GND to avoid

oscillation on this pin and extra current consumption.

37 ENGINE1 PC

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Program counter starting value for program execution engine 1; a value from 0000000 to 1011111. The

maximum value depends on program memory allocation between the three program execution engines.

38 ENGINE2 PC

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38 — Bits [6:0] PC

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Program counter starting value for program execution engine 2; a value from 0000000 to 1011111.

39 ENGINE3 PC

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39 — Bits [6:0] PC

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Program counter starting value for program execution engine 3; a value from 0000000 to 1011111.

LP5523 Datasheet(PDF) 33 Page - Texas Instruments

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