5.7 Device Electrical Characteristics

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN(1) TYP(2)

MAX

UNIT

LVTTL (EN, EN, 1A:4A)

|IIH|

High-level input current

VIH = 2 V or VCC

0

10

μA

|IIL|

Low-level input current

VIL = GND or 0.8 V

0

10

μA

Ci

Input capacitance

VI = 0.4 sin(30E6πt) + 0.5 V(3)

5

pF

M-LVDS (1Y/1Z:4Y/4Z)

|VYZ|

Differential output voltage magnitude

See Figure 6-2

480

650

mV

Δ|VYZ|

Change in differential output voltage magnitude

between logic states

–50

50

mV

VOS(SS)

Steady-state common-mode output voltage

See Figure 6-3

0.8

1.2

V

ΔVOS(SS)

Change in steady-state common-mode output

voltage between logic states

–50

50

mV

VOS(PP)

Peak-to-peak common-mode output voltage

150

mV

VY(OC)

Maximum steady-state open-circuit output

voltage

See Figure 6-7

0

2.4

V

VZ(OC)

Maximum steady-state open-circuit output

voltage

0

2.4

V

VP(H)

Voltage overshoot, low-to-high level output

See Figure 6-5

1.2 VSS

V

VP(L)

Voltage overshoot, high-to-low level output

–0.2 VSS

V

|IOS|

Differential short-circuit output current

magnitude

See Figure 6-4

24

mA

IOZ

High-impedance state output current

–1.4 V ≤ (VY or VZ) ≤ 3.8 V,

Other output = 1.2 V

–15

10

μA

IO(OFF)

Power-off output current

–1.4 V ≤ (VY or VZ) ≤ 3.8 V,

Other output = 1.2 V, VCC = 0 V

–10

10

μA

CY or CZ Output capacitance

VY or VZ = 0.4 sin(30E6πt) + 0.5 V,(3)

Other input at 1.2 V, driver disabled

3

pF

CYZ

Differential output capacitance

VYZ = 0.4 sin(30E6πt) V,(3)

Driver disabled

2.5

pF

CY/Z

Output capacitance balance, (CY/CZ)

0.99

1.01

(1)

The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

(2)

All typical values are at 25°C and with a 3.3-V supply voltage.

(3)

HP4194A impedance analyzer (or equivalent)

SN65MLVD047A

SLLS736B – JULY 2006 – REVISED MARCH 2024

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