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BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS

DRIVER SWITCHING CHARACTERISTICS

SN65MLVD201, SN65MLVD203

SN65MLVD206, SN65MLVD207

SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

VA = 3.8 V,

VB = 1.2 V,

0

32

Receiver or transceiver with driver

IA

VA = 0 V or 2.4 V,

VB = 1.2 V

–20

20

µA

disabled input current

VA = –1.4 V,

VB = 1.2 V

–32

0

VB = 3.8 V,

VA = 1.2 V

0

32

Receiver or transceiver with driver

IB

VB = 0 V or 2.4 V,

VA = 1.2 V

–20

20

µA

disabled input current

VB = –1.4 V,

VA = 1.2 V

–32

0

Receiver or transceiver with driver

IAB

disabled differential input current

VA = VB,

1.4

≤ VA ≤ 3.8 V

-4

4

µA

(IA – IB)

VA = 3.8 V,

VB = 1.2 V,

0 V

≤ VCC ≤ 1.5 V

0

32

Receiver or transceiver power-off

IA(OFF)

VA = 0 V or 2.4 V,

VB = 1.2 V,

0 V

≤ VCC ≤ 1.5 V

–20

20

µA

input current

VA = –1.4 V,

VB= 1.2 V,

0 V

≤ VCC ≤ 1.5 V

–32

0

VB = 3.8 V,

VA = 1.2 V,

0 V

≤ VCC ≤ 1.5 V

0

32

Receiver or transceiver power-off

IB(OFF)

VB = 0 V or 2.4 V,

VA = 1.2 V,

0 V

≤ VCC ≤ 1.5 V

–20

20

µA

input current

VB = –1.4 V,

VA = 1.2 V,

0 V

≤ VCC ≤ 1.5 V

–32

0

Receiver input or transceiver

IAB(OFF)

power-off differential input current

VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V

–4

4

µA

(IA – IB)

Transceiver with driver disabled input

CA

VA = 0.4 sin (30E6πt) + 0.5V

(2),

VB = 1.2 V

5

pF

capacitance

Transceiver with driver disabled input

CB

VB = 0.4 sin (30E6πt) + 0.5 V

(2),

VA = 1.2 V

5

pF

capacitance

Transceiver with driver disabled

CAB

VAB = 0.4 sin (30E6πt)V

(2)

3

pF

differential input capacitance

Transceiver with driver disabled input

CA/B

0.99

1.01

capacitance balance, (CA/CB)

(1)

All typical values are at 25

°C and with a 3.3-V supply voltage.

(2)

HP4194A impedance analyzer (or equivalent)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX UNIT

tPLH

Propagation delay time, low-to-high-level output

1

1.5

2.4

ns

tPHL

Propagation delay time, high-to-low-level output

1

1.5

2.4

ns

tr

Differential output signal rise time

1

1.6

ns

See Figure 5

tf

Differential output signal fall time

1

1.6

ns

tsk(p)

Pulse skew (|tPHL – tPLH|)

0

100

ps

tsk(pp)

Part-to-part skew(2)

1

ns

tjit(per)

Period jitter, rms (1 standard deviation)(3)

100 MHz clock input(4)

2

3

ps

tjit(pp)

Peak-to-peak jitter(3) (5)

200 Mbps 215–1 PRBS input(6)

30

130

ps

tPHZ

Disable time, high-level-to-high-impedance output

7

ns

tPLZ

Disable time, low-level-to-high-impedance output

7

ns

See Figure 6

tPZH

Enable time, high-impedance-to-high-level output

7

ns

tPZL

Enable time, high-impedance-to-low-level output

7

ns

(1)

All typical values are at 25

°C and with a 3.3-V supply voltage.

(2)

tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(3)

Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4)

tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.

(5)

Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).

(6)

tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.

Copyright © 2002–2007, Texas Instruments Incorporated

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