= 1

EXCLUSIVE OR

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8

SN74LVC1G86

SCES222Q – APRIL 1999 – REVISED JUNE 2017

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8 Detailed Description

8.1 Overview

The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input

exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

A common application is as a true and complement element. If the input is low, the other input is reproduced in

true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be

shown at any two ports.

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and

damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must

be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given

in the Electrical Characteristics, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating

Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a

device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS

input.