SDA

SDA

SCL

SCL

S

P

STARTCondition

STOP Condition

SDA

SCL

DataLine

Stable;

DataValid

Change

ofdata

allowed

12

TCA9543A

SCPS206B – MARCH 2014 – REVISED NOVEMBER 2019

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8.3 Feature Description

The TCA9543A is a dual channel bidirectional translating switch for I2C buses that supports Standard-Mode (100

kHz) and Fast-Mode (400 kHz) operation. The TCA9543A features I2C control using a single 8-bit control register

in which bits 1 and 0 control the enabling and disabling of the two switch channels of I2C data flow. The

TCA9543A also supports interrupt signals for each slave channel and this data is held in bits 5 and 4 of the

control register. Depending on the application, voltage translation of the I2C bus can also be achieved using the

TCA9543A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that

communication on the I2C bus enters a fault state, the TCA9543A can be reset to resume normal operation using

the RESET terminal feature or by a power-on reset which results from cycling power to the device.

8.4 Device Functional Modes

8.4.1

RESET Input

The RESET input can be used to recover the TCA9543A from a bus-fault condition. The registers and the I2C

state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL.

Both channels also are deselected in this case. RESET must be connected to VCC through a pull-up resistor.

8.4.2 Power-On Reset

When power is applied to VCC, an internal power-on reset holds the TCA9543A in a reset condition until VCC has

reached VPORR. At this point, the reset condition is released and the TCA9543A registers and I

2C state machine

are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must

be lowered below VPORF to reset the device.

8.5 Programming

8.5.1 I2C Interface

The I2C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial

data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup

resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not

busy.

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high

period of the clock pulse as changes in the data line at this time is interpreted as control signals (see Figure 8).

Figure 8. Bit Transfer

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the

clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is

defined as the stop condition (P) (see Figure 9).

Figure 9. Definition of Start and Stop Conditions