APPLICATION INFORMATION

GENERAL FUNCTION

2REF

CODE

0x1000

[V]

POWER ON RESET (POR)

SERIAL INTERFACE

SCLK

FS

DIN

SCLK

FS

F15

F15

X

X

E0

X

E1

E14

E15

D0

D1

D14

D15

X

DIN

F15

F15

X

X

E1

E0

E14

E15

X

D0

D1

D14

D15

X

DSP Mode:

µC Mode:

TLV5630

TLV5631

TLV5632

SLAS269F – MAY 2000 – REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com

The TLV5630/31/32 are 8-channel, single-supply DACs, based on a resistor string architecture. They consist of a

serial interface, a speed and power-down control logic, an internal reference, a resistor string, and a rail-to-rail

output buffer.

The output voltage (full scale determined by reference) for each channel is given by:

where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for

the TLV5630, 0x000 to 0xFFC for the TLV5631, and 0x000 to 0xFF0 for the TLV5632.

The built-in power-on-reset circuit controls the output voltage after power up. On power up, all latches including

the preset register are set to zero, but the DAC outputs are only set to zero if the LDAC is low. The DAC outputs

may have a small offset error produced by the output buffer. The registers remains at zero until a valid write

sequence is made to the DAC, changing the DAC register data. This is useful in applications where it is

important to know the state of the outputs of the DAC after power up. All digital inputs must be logic low until the

digital and analog supplies are applied. Any logic high voltages applied to the logic input pins when power is not

applied to AVDD and DVDD, may power the device logic circuit through the overvoltage protection diode causing

an undesired operation. When separate analog (AVDD) and digital (DVDD) supplies are used, AVDD must come up

first before DVDD, to ensure that the power-on-reset circuit operates correctly.

A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling

edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC

holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to

transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an

asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.

For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.

10

Submit Documentation Feedback

Copyright © 2000–2008, Texas Instruments Incorporated

Product Folder Link(s): TLV5630 TLV5631 TLV5632