DAC A-H AND TWO-CHANNEL REGISTERS

PRESET

TLV5630

TLV5631

TLV5632

SLAS269F – MAY 2000 – REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com

Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the

complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).

The TLV5630 decodes all 12 data bits. The TLV5631 decodes D11 to D2 (D1 and D0 are ignored). The TLV5632

decodes D11 to D4 (D3 to D0 are ignored).

The outputs of the DAC channels can be driven simultaneously to a predefined value stored in the preset register

by driving the PRE input pin low and asserting the LDAC input pin. The preset register is cleared (set to zero) by

the POR circuit after power up. Therefore, it must be written with a predefined value before asserting the PRE

pin low, unless zero is the desired preset value. The PRE input is asynchronous to the clock.

CTRL0

BIT

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Function

X

X

X

X

X

X

X

PD

DO

R1

R0

IM

Default

X

X

X

X

X

X

X

0

0

0

0

0

PD

: Full device power down

0 = normal

1 = power down

DO

: DOUT enable

0 = disabled

1 = enabled

R1:0

: Reference select bits

0 = external

1 = external, 2 = internal 1 V, 3 = internal 2 V

IM

: Input mode

0 = straight binary

1 = twos complement

X

: Reserved

If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to

daisy-chain multiple DACs on one serial bus.

CTRL1

BIT

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Function

X

X

X

X

PGH

PEF

PCD

PAB

SGH

SEF

SCD

SAB

Default

X

X

X

X

0

0

0

0

0

0

0

0

PXY

: Power Down DACXY

0 = normal

1 = power down

SXY

: Speed DACXY

0 = slow

1 = fast

XY

: DAC pair AB, CD, EF or GH

In power-down mode, the amplifiers of the selected DAC pair are disabled and the total power consumption of

the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by setting the PXY

bit within the data word to 1.

There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and

slow mode is selected by setting SXY to 0.

12

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