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Voltage Reference

Oscillator and PWM Ramp

Switching Frequency +

100 kW

R

500 [kHz]

(4)

Error Amplifier

PWM Control

TPS54611-EP, TPS54612-EP

TPS54613-EP, TPS54614-EP

TPS54615-EP, TPS54616-EP

SGLS293A – FEBRUARY 2005 – REVISED AUGUST 2005

The voltage reference system produces a precise, temperature-stable voltage from a bandgap circuit. A scaling

amplifier and DAC are then used to produce the reference voltages for each of the fixed output devices.

The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a

static digital input. If a different frequency of operation is required for the application, the oscillator frequency can

be externally adjusted from 280 kHz to 700 kHz by connecting a resistor from the RT pin to AGND and floating

the FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from

RT to AGND:

The following table summarizes the frequency selection configurations:

SWITCHING FREQUENCY

FSEL PIN

RT PIN

350 kHz, internally set

Float or AGND

Float

550 kHz, internally set

≥2.5 V

Float

Externally set 280 kHz to 700 kHz

Float

R = 180 k

Ω to 68 kΩ

Externally synchronized frequency(1)

Synchronization signal

R = RT value for 80% external synchronization fre-

quency

(1)

To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R

≤ 1 kΩ and C

≤ 120 pF.

The high performance, wide bandwidth, voltage error amplifier is gain-limited to provide internal compensation of

the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance

values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good

noise and ripple characteristics, but with exceptional transient response. Transient recovery times are typically in

the range of 10 µs to 20 µs.

Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.

Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator pulse train alternately set and reset the PWM latch.

Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse

width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to

charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the

error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and

turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM

ramp.

During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on

until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The

device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting

VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is

continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE

voltage decreases to a range that allows the PWM comparator to change states. The TPS54611-TPS54616

devices are capable of sinking current continuously until the output reaches the regulation set-point.

If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds

the error amplifier output. The high-side FET turns off and the low-side FET turns on to decrease the energy in

the output inductor and consequently decrease the output current. This process is repeated each cycle in which

the current limit comparator is tripped.

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