PARAMETER

TEST

CONDITIONS

(1)

VCC

25°C

–40°C to 85°C

–55°C to 125°C

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

IOZ

Three-state leakage

current

5.5

±0.5

±5.0

±10

µA

(1)

VI = VIH or VIL, unless otherwise noted.

(2)

For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.

(3)

Inputs held at VCC – 2.1.

5.5 Switching Characteristics

Input tt = 6ns. Unless otherwise specified, CL = 50pF

PARAMETER

VCC(V)

25°C

-40°C to

85°C

-55°C to

125°C

UNIT

TYP

MAX

MAX

MAX

HC TYPES

tpd

Propagation delay, clock to

output

2

200

250

300

ns

4.5

17

(1)

40

50

60

6

34

43

51

tpd

Propagation delay, MR to output

2

175

220

265

ns

4.5

12

(1)

35

44

53

6

30

37

45

tpd

Propagation delay output enable

to Q (Figure 6)

2

150

190

225

ns

4.5

12

(1)

30

38

45

6

26

33

38

tt

Output transition times

2

60

75

90

ns

4.5

12

15

18

6

10

13

15

fMAX

Maximum clock frequency

5

60

(1)

MHz

Ci

Input capacitance

10

10

10

pF

CO

Three-state output capacitance

10

10

10

pF

Cpd (2) (3)

Power dissipation capacitance

5

29

pF

HCT TYPES

tpd

Propagation delay, clock to

output

4.5

17

(1)

40

50

60

ns

tpd

Propagation delay, MR to output

4.5

18

(1)

44

55

66

ns

tpd

Propagation delay output enable

to Q (Figure 6)

2

150

190

225

ns

4.5

14

(1)

30

38

45

6

26

33

38

tt

Output transition times

4.5

15

19

22

ns

fMAX

Maximum clock frequency

5

60

(1)

MHz

Ci

Input capacitance

10

10

10

pF

Cpd (2) (3)

Power dissipation capacitance

5

34

pF

(1)

Typical value tested at 5V, CL = 15pF.

(2)

CPD is used to determine th edynamic power consumption, per package.

(3)

PD = VCC 2fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022

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