Figure 6-5. HC setup times, hold times, removal

time, and propagation delay times for edge

triggered sequential logic circuits

Figure 6-6. HCT setup times, hold times, removal

time, and propagation delay times for edge

triggered sequential logic circuits

Figure 6-7. HC three-state propagation delay

waveform

Figure 6-8. HCT three-state propagation delay

waveform

NOTE: Opend drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test

circuit is Output RL = 1kΩ to VCC, CL = 50pF

Figure 6-9. HC and HCT three-state propagation delay test circuit

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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173

SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022

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