DIX4192IPFBR datasheet(29/71 Pages) TI2

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DIX4192

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SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Figure 25. Register 03: Port A Control Register 1

7 (MSB)

0 (LSB)

AMUTE

AOUTS1

AOUTS0

AM/S

AFMT2

AFMT1

AFMT0

Table 6. Register 03: Port A Control Register 1 Field Descriptions

AFMT[2:0]

Port A Audio Data Format

These bits are used to set the audio input and output data format for Port A. Refer to Audio Serial Port Operation for illustrations of the

supported data formats. Refer to the Audio Serial Ports section of the Electrical Characteristics table and Figure 1 for an applicable timing

diagram and parameters.

AFMT2

AFMT1

AFMT0

Audio Data Format

24-Bit Left-Justified (default)

24-Bit Philips I2S

Unused

16-Bit Right-Justified

18-Bit Right-Justified

20-Bit Right-Justified

24-Bit Right-Justified

AM/S

Port A Slave and Master Mode

This bit is used to set the audio clock mode for Port A to either Slave or Master.

AM/S

Slave/Master Mode

Slave mode; the LRCK and BCK clocks are inputs generated by an external digital audio source. (default)

Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source.

AOUTS[1:0]

Port A Output Data Source

These bits are used to select the output data source for Port A. The data is output at SDOUTA (pin 40).

AOUTS1

AOUTS0

Output Data Source

Port A input, for data loop back. (default)

Port B input

DIR

Reserved

AMUTE

Port A Output Mute

This bit is used to mute the Port A audio data output.

AMUTE

Output Mute

Disabled; SDOUTA is driven by the output data source. (default)

Enabled; SDOUTA is forced low.

Figure 26. Register 04: Port A Control Register 2

7 (MSB)

0 (LSB)

ACLK1

ACLK0

ADIV1

ADIV0

Table 7. Register 04: Port A Control Register 2 Field Descriptions

ADIV[1:0]

Port A Master Clock Divider

These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation.

BCKA is always set to 64 times the LRCKA clock rate in Master mode.

ADIV1

ADIV0

Master Mode Clock Divider

Divide-by-128 (default)

Divide-by-256

Divide-by-384

Divide-by-512

ACLK[1:0]

Port A Master Clock Source

These bits are used to set the master clock source for Port A when configured for Master mode operation.

ACLK1

ACLK0

Master Clock Source

MCLK (default)

RXCKI

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