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DIX4192IPFBR Datasheet(PDF) 7 Page - Texas Instruments |
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DIX4192IPFBR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 71 page  7 DIX4192 www.ti.com SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016 Product Folder Links: DIX4192 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Electrical Characteristics (continued) All specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The typical VIO supply current is measured using the DIX4192EVM evaluation module with loading from the DAIMB mother-board circuitry. VIO supply current is dependent upon the loading on the logic output pins. fRXCKOD Recovered clock output (RXCKO) duty cycle 45% 55% Recovered clock output (RXCKO) intrinsic jitter Measured cycle-to-cycle 250 ps RMS DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) Intrinsic output jitter Measured cycle-to-cycle 200 ps RMS POWER SUPPLIES Supply current: initial startup All blocks powered down by default IDD18S VDD18 = 1.8 V 10 μA IDD33S VDD33 = 3.3 V 10 μA IIOS VIO = 3.3 V 300 μA ICCS VCC = 3.3 V 10 μA Supply current: quiescent All blocks powered up with no clocks applied IDD18Q VDD18 = 1.8 V 2.3 mA IDD33Q VDD33 = 3.3 V 0.6 mA IIOQ VIO = 3.3 V 0.3 mA ICCQ VCC = 3.3 V 6.3 mA Supply current: dynamic All blocks powered up, fS = 48 kHz IDD18D VDD18 = 1.8 V 5.1 mA IDD33D VDD33 = 3.3 V 14.1 mA IIOD(1) VIO = 3.3 V 46 mA ICCD VCC = 3.3 V 7.4 mA Supply current: high sampling rate All blocks powered up, fS = 192 kHz IDD18H VDD18 = 1.8 V 6.7 mA IDD33H VDD33 = 3.3 V 15 mA IIOH(1) VIO = 3.3 V 47 mA ICCH VCC = 3.3 V 7.5 mA Total power dissipation: initial startup All blocks powered down by default 1 mW Total power dissipation: quiescent All blocks powered up with no clocks applied 28 mW Total power dissipation: dynamic All blocks powered up, fS = 48 kHz 233 mW Total power dissipation: high sampling rate All blocks powered up, fS = 192 kHz 242 mW 8.6 Timing Requirements MIN NOM MAX UNIT AUDIO SERIAL PORTS (PORT A AND PORT B) fLRCK LRCK clock frequency 0 216 kHz tLRCKD LRCK clock duty cycle 50% fBCK BCK clock frequency 0 13.824 MHz tBCKH BCK high pulse width 10 ns tBCKL BCK low pulse width 10 ns tAIS Audio data Input (SDIN) set-up time 10 ns tAISH Audio data input (SDIN) hold time 10 ns tADD Audio data output (SDOUT) delay 10 ns HOST INTERFACE: SPI MODE fCCLK Serial clock (CCLK) frequency 0 40 MHz tCSCR CS falling to CCLK rising 8 ns tCFCS CCLK falling to CS rising 7 ns tCDS CDIN data set-up time 7 ns |
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