LP38501-ADJ, LP38503-ADJ

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SNVS522I – AUGUST 2007 – REVISED AUGUST 2015

8.2.2.5 RFI/EMI Susceptibility

Radio frequency interference (RFI) and electro-magnetic interference (EMI) can degrade any integrated circuit's

performance because of the small dimensions of the geometries inside the device. In applications where circuit

sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must

be taken to ensure that this does not affect the device regulator.

If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes

from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the

device to reduce the amount of EMI conducted into the device.

If the LP38501-ADJ or LP38503-ADJ output is connected to a load which switches at high speed (such as a

clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the device

output. Because the bandwidth of the regulator loop is less than 300 kHz, the control circuitry cannot respond to

load changes above that frequency. This means the effective output impedance of the device at frequencies

above 300 kHz is determined only by the output capacitor(s). Ceramic capacitors provide the best performance

in this type of application.

In applications where the load is switching at high speed, the output of the device may need RF isolation from

the load. In such cases, it is recommended that some inductance be placed between the output capacitor and

the load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in high

noise environments, because RFI/EMI is easily radiated directly into PC traces. Noisy circuitry must be isolated

from clean circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes

begin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multi-layer PC Board

applications, care must be taken in layout so that noisy power and ground planes do not radiate directly into

adjacent layers which carry analog power and ground.

8.2.2.6 Output Noise

Noise is specified in two ways:

•

Spot noise or output noise density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a

function of frequency.

•

Total output noise or broadband noise is the RMS sum of spot noise over a specified bandwidth, usually

several decades of frequencies.

Spot noise is measured in units µV/

√Hz or nV/√Hz and total output noise is measured in µV(RMS). The primary

source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low-

frequency component and a high frequency component, which depend strongly on the silicon area and quiescent

current.

Noise can generally be reduced in two ways: by increasing the transistor area or increasing the reference

current. However, enlarging the transistors increases die size, and increasing the reference current means higher

total supply current (GND pin current).

8.2.2.7 Power Dissipation/Heatsinking

The maximum power dissipation (PD(MAX)) of the LP38501-ADJ and LP38503-ADJ is limited by the maximum

junction temperature of 125°C, along with the maximum ambient temperature (TA(MAX)) of the application, and the

thermal resistance (RθJA) of the package. Under all possible conditions, the junction temperature (TJ) must be

within the range specified in the Recommended Operating Conditions. The total power dissipation of the device

is given by:

PD = ((VIN − VOUT) × IOUT) + (VIN × IGND)

where

•

IGND is the operating ground current of the device (specified under Electrical Characteristics).

(3)

The maximum allowable junction temperature rise (

ΔTJ) depends on the maximum expected ambient

temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)):

ΔTJ = TJ(MAX)− TA(MAX)

(4)

The maximum allowable value for junction-to-ambient thermal resistance, RθJA, can be calculated using the

formula:

RθJA = ΔTJ / PD(MAX)

(5)

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