t(BCH)

DOUT (Output)

t(BCL)

t(BL)

t(BCY)

50% of VDD

50% of VDD

50% of VDD

LRCK (Output)

BCK (Output)

DIN (Input)

t(DH)

t(DS)

50% of VDD

t(BD)

t(LD)

T0010-05

SYSCK

(Output)

LRCK

(Output)

BCK

(Output)

t

(SLL)

t

(SBH)

t

(SBL)

t

(SLH)

T0196-01

PCM2704

,, PCM2705

PCM2706, PCM2707

SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

SYMBOL

PARAMETER

MIN

MAX

UNIT

t(BCY)

BCK pulse cycle time

300

ns

t(BCH)

BCK pulse duration, HIGH

100

ns

t(BCL)

BCK pulse duration, LOW

100

ns

t(BL)

LRCK delay time from BCK falling edge

–20

40

ns

t(BD)

DOUT delay time from BCK falling edge

–20

40

ns

t(LD)

DOUT delay time from LRCK edge

–20

40

ns

t(DS)

DIN setup time

20

ns

t(DH)

DIN hold time

20

ns

NOTE: Load capacitance of LRCK, BCK, and DOUT is 20 pF.

Figure 23. Audio Interface Timing

SYMBOL

PARAMETER

MIN

MAX

UNIT

t(SLL), t(SLH)

LRCK delay time from SYSCK rising edge

–5

10

ns

t(SBL), t(SBH)

BCK delay time from SYSCK rising edge

–5

10

ns

NOTE: Load capacitance is 20 pF.

Figure 24. Audio Clock Timing

20

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