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TLV2252QDREP Datasheet(PDF) 29 Page - Texas Instruments |
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TLV2252QDREP Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 41 page ![]() TLV225xEP, TLV225xAEP Advanced LinCMOS RAILTORAIL VERY LOW POWER OPERATIONAL AMPLIFIERS SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006 29 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION driving large capacitive loads The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56 and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins (Rnull = 0). A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins when driving large capacitive loads. Figure 55 and Figure 56 show the effects of adding series resistances of 10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects – the first adds a zero to the transfer function and the second reduces the frequency of the pole associated with the output load in the transfer function. The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the improvement in phase margin, equation 1 can be used. ∆φ m1 + tan –1 2 ×π × UGBW × R null × C L ∆φ m1 UGBW R null C L (1) Where : = improvement in phase margin = unity-gain bandwidth frequency = output series resistance = load capacitance The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To use equation 1, UGBW must be approximated from Figure 58. Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The overestimation is caused by the decrease in the frequency of the pole associated with the load, providing additional phase shift and reducing the overall improvement in phase margin. Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to optimize the design of circuits driving large capacitance loads. 50 k Ω 50 k Ω VDD −/ GND VDD + Rnull CL VI + − Figure 60. Series-Resistance Circuit |
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