CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features

• AC types feature 1.5V to 5.5V operation and

balanced noise immunity at 30% of the supply

voltage

• Speed of bipolar F, AS, and S, with significantly

reduced power consumption

• Balanced propagation delays

• ±24mA output drive current

– Fanout to 15 F devices

• SCR-latchup-resistant CMOS process and circuit

design

• Exceeds 2kV ESD protection per MIL-STD-883,

method 3015

2 Description

The

CD74AC109-Q1

device

contains

two

independent J-K positive edge triggered flip-flops. A

low level at the preset (PRE) or clear (CLR) inputs

sets or resets the outputs, regardless of the levels of

the other inputs. When PRE and CLR are inactive

(high), data at the J and K inputs that meets the

setup-time requirements is transferred to the outputs

on the positive-going edge of the clock (CLK) pulse.

The device is qualified for automotive applications.

Device Information

PART NUMBER

PACKAGE(1)

BODY SIZE(2)

CDx4AC109

D (SOIC, 16)

9.90mm x 3.90mm

N (PDIP, 16)

19.3mm x 6.35mm

J (CDIP, 16)

19.56mm x 6.92mm

(1)

For more information, see Mechanical, Packaging, and

Orderable Information.

(2)

The body size (length × width) is a nominal value and does

not include pins.

PRE

CLK

J

CLR

Q

Q

C

C

C

C

K

TG

TG

TG

TG

C

C

C

C

C

C

Copyright © 2016, Texas Instruments Incorporated

Logic Diagram

CD54AC109, CD74AC109

SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.