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AMC1336

SBAS951B – AUGUST 2019 – REVISED APRIL 2020

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Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and

fCLKIN = 20 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(2)

Offset error drift is calculated using the box method, as described by the following equation:

TCEO = (valueMAX - valueMIN) / TempRange

(3)

The typical value includes one sigma statistical variation.

(4)

Gain error drift is calculated using the box method, as described by the following equation:

TCEG (ppm) = ((valueMAX - valueMIN) / (value x TempRange)) X 10

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DC ACCURACY

Resolution

Decimation filter output set to 16 bits

16

Bit

INL

Integral nonlinearity(1)

Resolution: 16 bits

–4

±1.6

4

LSB

EO

Offset error

Initial, at TA = 25°C, AINP = AINN = AGND

–0.5

±0.03

0.5

mV

TCEO

Offset error drift(2)

–4

±0.6

4

µV/°C

EG

Gain error(3)

Initial, at TA = 25°C,

VAINP = 1 V or VAINN = –1 V, AINN = AGND

–0.25

±0.02

0.25

%

TCEG

Gain error drift(4)

–40

±20

40

ppm/°C

CMRR

Common-mode rejection ratio

AINP = AINN, fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max

–104

dB

AINP = AINN, fIN = 10 kHz, –0.5 V ≤ VIN ≤ 0.5 V

–96

PSRR

Power-supply rejection ratio

PSRR vs AVDD, at DC

–83

dB

PSRR vs AVDD, 100-mV and 10-kHz ripple

–83

AC ACCURACY

SNR

Signal-to-noise ratio

VIN = 2 VPP, fIN = 1 kHz

82

87

dB

SINAD

Signal-to-noise + distortion

VIN = 2 VPP, fIN = 1 kHz

79

85

dB

THD

Total harmonic distortion

VIN = 2 VPP, fIN = 1 kHz

–91

–80

dB

SFDR

Spurious-free dynamic range

VIN = 2 VPP, fIN = 1 kHz

80

92

dB

DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)

IIN

Input current

DGND

≤ VIN ≤ DVDD

7

µA

CIN

Input capacitance

4

pF

VIH

High-level input voltage

0.7 x DVDD

DVDD + 0.3

V

VIL

Low-level input voltage

–0.3

0.3 x DVDD

V

DIGITAL OUTPUT (CMOS)

CLOAD

Output load capacitance

fCLKIN = 21 MHz

15

30

pF

VOH

High-level output voltage

IOH = –20 µA

DVDD – 0.1

V

IOH = –4 mA

DVDD – 0.4

VOL

Low-level output voltage

IOL = 20 µA

0.1

V

IOL = 4 mA

0.4

POWER SUPPLY

AVDDPOR

AVDD power-on reset threshold voltage

AVDD falling

2.4

2.6

2.8

V

IAVDD

High-side supply current

3 V

≤ AVDD ≤ 3.6 V

6.8

9

mA

4.5 V

≤ AVDD ≤ 5.5 V

7.8

10.5

IDVDD

Controller-side supply current

2.7 V

≤ DVDD ≤ 3.6 V, CLOAD = 15 pF

3.4

5

mA

4.5 V

≤ DVDD ≤ 5.5 V, CLOAD = 15 pF

3.7

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