AD6653 datasheet(46/80 Pages) AD

46 / 80 page

AD6653

Rev. 0 | Page 46 of 80

Addr.

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

0x0D

Test Mode

(Local)

Open

Reset

PN long

sequence

Reset

PN short

sequence

Open

Output test mode

000 = off (default)

001 = midscale short

010 = positive FS

011 = negative FS

100 = alternating

checkerboard

101 = PN long sequence

110 = PN short sequence

111 = one/zero word toggle

0x00

When

enabled, the

test data is

placed on

the output

pins

in place of

ADC output

data

0x10

Offset

Adjust

(Local)

Open

Offset adjust in LSBs from +31 to −32 (twos complement format)

0x00

0x14

Output Mode

Drive

strength

0 V to 3.3 V

CMOS or

ANSI

LVDS

1 V to 1.8 V

CMOS or

reduced

LVDS

(global)

Output

type

0 = CMOS

1 = LVDS

(global)

Interleaved

CMOS

(global)

Output

enable

bar

(local)

Open

Output

invert

(local)

00 = offset binary

01 = twos complement

01 = gray code

11 = offset binary

(local)

0x00

Configures

the outputs

and the

format of

the data

0x16

Clock Phase

Control

(Global)

Invert

DCO clock

Open

Input clock divider phase adjust

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

0x00

Allows

selection of

clock delays

into the

input clock

divider

0x17

DCO Output

Delay

(Global)

Open

DCO clock delay

(delay = 2500 ps × register value/31)

00000 = 0 ps

00001 = 81 ps

00010 = 161 ps

…

11110 = 2419 ps

11111 = 2500 ps

0x00

0x18

VREF Select

(Global)

Reference voltage

selection

00 = 1.25 V p-p

01 = 1.5 V p-p

10 = 1.75 V p-p

11 = 2.0 V p-p

(default)

Open

0xC0

Digital Feature Control Registers

0x100

Sync Control

(Global)

Signal

monitor

sync

enable

Half-band

next sync

only

Half-band

sync

enable

NCO32

sync only

NCO32

sync

enable

Clock

divider next

sync only

Clock

divider

sync

enable

Master

sync

enable

0x00

0x101

fS/8 Output

Mix Control

(Global)

Open

fS/8 start state

Open

fS/8 next

sync only

fS/8 sync

enable

0x00

0x102

FIR Filter

and Output

Mode

Control

(Global)

Open

FIR gain

0 = gain of

1 = gain of

fS/8 output

mix disable

Complex

output

enable

FIR filter

enable

0x00

0x103

Digital Filter

Control

(Global)

Open

Half-band

decimation

phase

Spectral

reversal

High-pass/

low-pass

select

Open

0x01

0x104

Fast Detect

Control

(Local)

Open

Fast Detect Mode Select[2:0]

Fast

detect

enable

0x00

AD6653 Datasheet(PDF) 46 Page - Analog Devices

AD6653 Datasheet(HTML) 46 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL