AD6653 datasheet(29/80 Pages) AD

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AD6653

Rev. 0 | Page 29 of 80

100

1000

INPUT FREQUENCY (MHz)

3.00ps

0.05ps

0.20ps

0.50ps

1.00ps

1.50ps

2.00ps

2.50ps

MEASURED

Figure 63. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD6653.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Refer to Application Note AN-501 and Application Note AN-756

for more information about jitter performance as it relates to

ADCs (see www.analog.com).

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 64 and Figure 65, the power dissipated by

the AD6653 is proportional to its sample rate. In CMOS output

mode, the digital power dissipation is determined primarily by the

strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated by

IDRVDD = VDRVDD × fCLK × N

where N is the number of output bits (26, in the case of the

AD6653, assuming the FD bits are inactive).

This maximum current occurs when every output bit switches on

every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of fCLK/2. In practice, the DRVDD current is established

by the average number of output bits switching, which is deter-

mined by the sample rate and the characteristics of the analog

input signal. Reducing the capacitive load presented to the output

drivers can minimize digital power consumption. The data in

Figure 64 and Figure 65 was taken using the same operating

conditions as those used for the Typical Performance

Characteristics, with a 5 pF load on each output driver.

1.50

1.25

1.00

0.75

0.50

0.25

0.6

IAVDD

IDVDD

IDRVDD

0.5

0.4

0.3

0.2

0.1

100

150

125

SAMPLE RATE (MSPS)

TOTAL POWER

Figure 64. AD6653-150 Power and Current vs. Sample Rate

1.50

1.25

1.00

0.75

0.50

0.25

0.6

IAVDD

IDVDD

IDRVDD

0.5

0.4

0.3

0.2

0.1

050

100

125

SAMPLE RATE (MSPS)

TOTAL POWER

Figure 65. AD6653-125 Power and Current vs. Sample Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD6653 is placed in power-down

mode. In this state, the ADC typically dissipates 2.5 mW.

During power-down, the output drivers are placed in a high

impedance state. Asserting the PDWN pin low returns the

AD6653 to its normal operating mode. Note that PDWN is

referenced to the digital output driver supply (DRVDD) and

should not exceed that supply voltage level. PDWN can be

driven with 1.8 V logic, even when DRVDD is at 3.3 V.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, the wake-up time is related to

the time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

AD6653 Datasheet(PDF) 29 Page - Analog Devices

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