STM32U073RCU3 datasheet(93/146 Pages) STMICROELECTRONICS

93 / 146 page

Figure 26. ADC accuracy characteristics

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End-point correlation line

n = ADC resolution

ET = total unadjusted error: maximum deviation

between the actual and ideal transfer curves

EO = offset error: maximum deviation between the first

actual transition and the first ideal one

EG = gain error: deviation between the last ideal

transition and the last actual one

ED = differential linearity error: maximum deviation

between actual steps and the ideal one

EL = integral linearity error: maximum deviation between

any actual transition and the end point correlation line

2n-1

Output code

VSSA

2n-2

2n-3

VREF+ (VDDA)

1 LSB ideal

(1)

(2)

(3)

(or

)]

[1LSB =

VDDA

VREF+

Figure 27. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch

function

Sample-and-hold ADC converter

Converter

Cparasitic(2)

Ilkg(3)

CADC

VDDA(4)

RAIN(1)

VAIN

RADC

VREF+(4)

VSSA

I/O

analog

switch

Sampling

switch with

multiplexing

VSS

1. Refer to Table 70. ADC characteristics for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad

capacitance (refer to Table 64. I/O static characteristics for the value of the pad capacitance). A high Cparasitic

value downgrades conversion accuracy. To remedy this, fADC should be reduced.

3. Refer to Table 64. I/O static characteristics for the values of Ilkg.

4. Refer to Section 3.6.1: Power supply schemes.

6.3.18.1

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13. Power supply scheme. The 100 nF

capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

STM32U073x8/B/C

Electrical characteristics

DS14548 - Rev 2

page 93/146

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