STM32U073RCI3TR datasheet(7/146 Pages) STMICROELECTRONICS

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Functional overview

3.1

Arm® Cortex®-M0+ core with MPU

The Arm Cortex -M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded

applications. It offers significant benefits to developers, including:

•

A simple architecture, easy to learn and program

•

ultra-low power, energy-efficient operation

•

Excellent code density

•

Deterministic, high-performance interrupt handling

•

Upward compatibility with Cortex-M processor family

•

Platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von

Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful

instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle

multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a

higher code density than other 8-bit and 16-bit microcontrollers.

Owing to embedded Arm core, the STM32U073x8/B/C devices are compatible with Arm tools and software.

The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in

Section 3.14.1: Nested vectored interrupt controller (NVIC).

3.2

Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M0+

processors. It balances the inherent performance advantage of the Arm Cortex-M0+ over flash memory

technologies, which normally requires the processor to wait for the flash memory at higher frequencies.

To release the processor near 67 DMIPS performance at 56 MHz, the accelerator implements an instruction

prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory.

Based on benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state

program execution from flash memory at a CPU frequency up to 56 MHz.

3.3

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to

corrupt accidentally the memory or resources used by any other active task.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the

misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program

accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS

environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 2

page 7/146

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