STM32U073RCU6TR datasheet(17/146 Pages) STMICROELECTRONICS

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3.12

Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.

With seven channels, it performs data transfers between memory-mapped peripherals and/or memories, to

offload the CPU.

Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes

an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

•

Single-AHB master

•

Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-peripheral data

transfers

•

Access, as source and destination, to on-chip memory-mapped devices such as flash memory, SRAM, and

AHB and APB peripherals

•

All DMA channels independently configurable:

–

Each channel is associated either with a DMA request signal coming from a peripheral, or with a

software trigger in memory-to-memory transfers. This configuration is done by software.

–

Priority between the requests is programmable by software (four levels per channel: very high, high,

medium, low) and by hardware in case of equality (such as request to channel 1 has priority over

request to channel 2).

–

Transfer size of source and destination are independent (byte, half-word, word), emulating packing

and unpacking. Source and destination addresses must be aligned on the data size.

–

Support of transfers from/to peripherals to/from memory with circular buffer management

–

Programmable number of data to be transferred: 0 to 216 - 1

•

Generation of an interrupt request per channel. Each interrupt request originates from any of the three

DMA events: transfer complete, half transfer, or transfer error.

3.13

DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA

controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its

DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable

events on its input trigger signals.

3.14

Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The

Cortex®-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event

controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events

such as, for example, a division by zero and, core-external events such as logical level changes on physical lines.

Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the

original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and

unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt

service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-

multiple and store-multiple operations significantly increases the device’s responsiveness in processing

exceptions.

3.14.1

Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line

events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex®-M0+ exceptions. It

provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and

start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the

NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base

address and the ISR order number used as offset.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 2

page 17/146

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