STA529Q datasheet(23/57 Pages) STMICROELECTRONICS

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STA529

PLL

Doc ID 13095 Rev 3

23/57

When automatic settings are not used, the PLL must be configured to generate an internal

frequency, fPHI, of N * fs, where fs is the frequency of pin LRCLKI. Values for N are given in

Table 15.

Example 1

fXTI = 13 MHz and fs = 44.1 kHz

IDF should be equal to 3 otherwise LDF becomes less than 8 (FRAC_CTRL must be 1):

LDF = floor(45.1584 / (13 / IDF)) = 10

FRACT = round([(45.1584 / (13 / IDF)) - floor(45.1584 / (13 / IDF))] * 216) = 27602.

where:

floor means rounded down and

round means rounded to nearest integer.

Using the above configuration, the system clock is 45.15841675 MHz, the approximate

static error is 16 Hz (that is, 0.5 ppm).

Example 2

fXTI = 19.2 MHz and fs = 48 kHz

IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1):

LDF = floor(49.152 / (19.2 / IDF)) = 10

FRACT = round([(49.152 / (19.2 / IDF)) - floor(49.152 / (19.2 / IDF))] * 216) = 15728.

Using the above configuration, the system clock is 49.151953125 MHz, the approximate

static error is 47 Hz (that is, 1 ppm).

Table 15.

Oversampling table

fs (kHz)

fPHI (MHz)

4096

32.768

11.025

4096

45.1584

4096

49.152

2048

32.768

22.05

2048

45.1584

2048

49.152

1024

32.768

44.1

1024

45.1584

1024

49.152

512

32.768

88.2

512

45.1584

512

49.152

128

256

32.768

176.4

256

45.1584

192

256

49.152

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