7.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will

optimize performance. This can be accomplished by providing short, appropriately sized traces from the

CDx4ACT151 to one or more of the receiving devices.

3. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum

output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive

load measured in MΩ; much larger than the minimum calculated previously.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

7.2.3 Application Curve

CBA

G

Y

b000

b010

b001

b000

D0

D1

D2

Figure 7-2. Application Timing Diagram

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CD54ACT151, CD74ACT151

SCHS338B – MARCH 2003 – REVISED MAY 2025

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