DAC7760IPWPR datasheet(35/69 Pages) TI2

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8.3.12 Programmable Slew Rate

The slew rate control feature controls the rate at which the output voltage or current changes. With the slew

rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the

attached load.

To reduce the slew rate, enable the slew rate control feature through bit 4 of Table 8-17. With this feature

enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate

defined by bits [7:5] (SRSTEP) and bits [11:8] (SRCLK) of the control register. SRCLK defines the rate at which

the digital slew updates; SRSTEP defines the amount by which the output value changes at each update. If the

DAC data register is read while the DAC output is still changing, the instantaneous value is read. Table 8-5 lists

the slew rate step-size options. Table 8-6 summarizes the slew rate update clock options.

Table 8-5. Slew Rate Step-Size (SRSTEP) Options

SRSTEP

STEP SIZE (LSB)

DAC7760

DAC8760

000

0.0625

001

0.125

010

0.25

011

0.5

100

101

110

111

128

Table 8-6. Slew Rate Update Clock (SRCLK) Options

SRCLK

DAC UPDATE FREQUENCY (Hz)

0000

258,065

0001

200,000

0010

153,845

0011

131,145

0100

115,940

0101

69,565

0110

37,560

0111

25,805

1000

20,150

1001

16,030

1010

10,295

1011

8,280

1100

6,900

1101

5,530

1110

4,240

1111

3,300

www.ti.com

DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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