DAC7760IPWPR datasheet(41/69 Pages) TI2

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Table 8-15 shows the register read addresses available on the DACx760 devices.

Table 8-15. Register Read Address Functions

READ

ADDRESS(1)

FUNCTION

XX XX00

Read status register

XX XX01

Read DAC data register

XX XX10

Read control register

00 1011

Read configuration register

01 0011

Read DAC gain calibration register

01 0111

Read DAC zero calibration register

(1)

X denotes don't care bits.

8.5.1.4 Stand-Alone Operation

SCLK can operate in either continuous or burst mode as long as the LATCH rising edge occurs after the

appropriate number of SCLK cycles. Providing more than or less than 24 SCLK cycles before the rising edge of

LATCH results in incorrect data being programmed into the device registers and incorrect data sent out on SDO.

The rising edge of SCLK that clocks in the MSB of the 24-bit input frame marks the beginning of the write cycle,

and data are written to the addressed registers on the rising edge of LATCH.

8.5.1.5 Multiple Devices on the Bus

Communication with the device is not directly gated by LATCH; therefore, do not connect multiple devices in

parallel without gating SCLK. Figure 8-9 shows two devices with SCLK gated for each device.

SCLK

DIN

DOUT

CS2

Microcontroller

CS1

Device 1

SCLK

LATCH1

SDO

DIN

Device 2

SCLK

LATCH2

SDO

DIN

Figure 8-9. Multiple Devices on the Bus Using Gated SCLK

The microcontroller uses two chip select lines, one for each LATCH pin. Each line is used to gate the SCLK for

communication for each device.

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DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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