DAC8760IPWPR datasheet(48/69 Pages) TI2

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After the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of

amplifier A2 and would therefore be seen across the 40-Ω resistor. To generate a 1-mA signal on the output

would therefore require a 40-mV peak-to-peak signal on CAP2. Because most HART modems do not output a

40-mV signal, a capacitive divider is used in the above circuit to attenuate the FSK signal from the modem. In

the above circuit, the high-pass cutoff frequency would be 1 / (2 × π × [R2+12.5 kΩ] × [C1 + C2]). There is one

disadvantage of this approach: if the AVDD supply was not clean, any ripple on it could couple into the part.

9.1.2.2 Using the ISET-R Pin

The second method to implement HART is to couple the HART signal through the ISET-R pin when IOUT is

operated using an external RSET resistor. The FSK signal from the modem is ac coupled into the pin through a

series combination of Rin and Cin as shown in Figure 9-4.

DAC

CAP1

CAP2

AVDD

IOUT

ISET-R

HART Signal

Conditioning

HART-IN

(ON Only in 4-mA

to 20-mA Range)

Cin

HART SIGNAL

RSET

15 NŸ

Rin

Figure 9-4. Implementing HART With the ISET-R pin

The magnitude of the ac current output is calculated as (VHART × k) / Rin, where k is a constant that represents

the gain transfer function from the ISET-R pin to the IOUT pin and depends on the selected current output range

as follows: k = 60 for the 4-mA to 20-mA range, 75 for the 0-mA to 20-mA range, and 90 for the 0-mA to 24-mA

range. The series input resistor and capacitor form a high-pass filter at the ISET-R pin and Cin must be selected

to make sure that all signals in the HART extended-frequency band pass through unattenuated.

9.1.3 Short-Circuit Current Limiting

The DACx760 voltage output includes an internal circuit to typically regulate the load current to about 30 mA.

However, this parameter is not production tested or trimmed. Optionally, use an external current limiting circuit

on VOUT. However, if the VOUT, IOUT and +VSENSE pins are tied together, this circuit must be placed in

the VOUT path before the circuit is tied together to the other pins at the common pin. The nature of the

current-limiting circuit depends on the application and load. An example of a unidirectional current limiter is

shown in Figure 9-5.

VIN

VOUT

Figure 9-5. Unidirectional Current Limiter Circuit

DAC7760, DAC8760

SBAS528D – JUNE 2013 – REVISED DECEMBER 2021

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DAC8760IPWPR Datasheet(PDF) 48 Page - Texas Instruments

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