VNF9Q20FTR datasheet(4/111 Pages) STMICROELECTRONICS

4 / 111 page

Figure 2. Connection diagram

OUTPUT2

N.C.

OUTPUT3

N.C.

STDBY_NOT

VREG

GND

10 11 12 13 14 15 16

26 25

28 27

30 29

32 31

N.C.

*: Electrically connected to TAB. Those pins are intented for thermo-mechanical purpose only.

They have to be soldered, but must be electrically isolated at PCB level.

TAB*

Table 1. Pin functionality description

Pin #

Name

Function

TAB

VCC

Battery connection: this is the backside TAB and is the direct connection to drain Power

MOSFET switches.

1, 2, 5-8, 20, 23,

24-26, 31, 32

N.C.

Not connected pin.

3, 4

OUTPUT2

Power OUTPUT 2: direct connection to the source Power MOSFET channel 2.

9, 10

DI0, DI1

Direct input: direct control for OUTx in limp-home mode. Configurable as OR combination

with the relevant SPI OUTx control bit in normal mode.

PWM_CLK

External clock of PWM engine.

CSN

Chip select not (active low): it is the selection pin of the device. It is a CMOS compatible

input.

SCK

Serial clock: it is a CMOS compatible input.

SDI

Serial data input: transfers data to be written serially into the device on the SCK rising edge.

SDO

Serial data output: transfers data serially out of the device on the SCK falling edge.

VDD

DC supply input for the SPI interface. 3.3 V and 5 V compatible.

VNF9Q20F

Block diagram and pin description

DS13909 - Rev 8

page 4/111

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