LPC2387 datasheet(28/47 Pages) NXP

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LPC2387_2

Product data sheet

Rev. 02 — 1 February 2008

28 of 47

NXP Semiconductors

LPC2387

Fast communication chip

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufﬁcient amplitude to drive the clock logic. The amount of time depends on many factors,

including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its

electrical characteristics (if a quartz crystal is used), as well as any other external circuitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.24.4 Power control

The LPC2387 supports a variety of power control features. There are four special modes

of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU

clock rate may also be controlled as needed by changing clock sources, reconﬁguring PLL

values, and/or altering the CPU clock divider value. This allows a trade-off of power versus

processing speed based on application requirements. In addition, Peripheral Power

Control allows shutting down the clocks to individual on-chip peripherals, allowing ﬁne

tuning of power consumption by eliminating all dynamic power use in any peripherals that

are not required for the application. Each of the peripherals has its own clock divider which

provides even better power control.

The LPC2387 also implements a separate power domain in order to allow turning off

power to the bulk of the device while maintaining operation of the RTC and a small SRAM,

referred to as the Battery RAM.

7.24.4.1

Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.24.4.2

Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The

processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Sleep mode and the logic levels of chip pins remain static. The

output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The

32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The CCLK and

USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or

certain speciﬁc interrupts that are able to function without clocks. Since all dynamic

operation of the chip is suspended, Sleep mode reduces chip power consumption to a

very low value. The ﬂash memory is left on in Sleep mode, allowing a very quick wake-up.

On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code

execution and peripherals activities will resume after 4 cycles expire. If the main external

oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconﬁgure the PLL and clock dividers accordingly.

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