LM46002PWPRG4 datasheet(5/54 Pages) TI2

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LM46002

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SNVSA13C – APRIL 2014 – REVISED APRIL 2019

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(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 2 W power dissipation.

(3)

RθJA is highly related to PCB layout and heat sinking. See Figure 101 for measured RθJA vs PCB area from a 2-layer board and a 4-

layer board.

6.4 Thermal Information

THERMAL METRIC(1)(2)

LM46002

UNIT

PWP (HTSSOP)

16 PINS

RθJA

Junction-to-ambient thermal resistance

38.9(3)

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

24.3

°C/W

RθJB

Junction-to-board thermal resistance

19.9

°C/W

ψJT

Junction-to-top characterization parameter

0.7

°C/W

ψJB

Junction-to-board characterization parameter

19.7

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

1.7

°C/W

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PINS)

ISHDNVIN-MIN-ST

Minimum input voltage for start-up

3.8

Shutdown quiescent current

VEN = 0 V

2.3

µA

IQ-NONSW

Operating quiescent current (non-

switching) from VIN

VEN = 3.3 V

VFB = 1.5 V

VBIAS = 3.4 V external

µA

IBIAS-NONSW

Operating quiescent current (non-

switching) from external VBIAS

VEN = 3.3 V

VFB = 1.5 V

VBIAS = 3.4 V external

135

µA

IQ-SW

Operating quiescent current (switching)

VEN = VIN

IOUT = 0 A

RT = open

VBIAS = VOUT = 3.3 V

RFBT = 1 Meg

µA

ENABLE (EN PIN)

VEN-VCC-H

Voltage level to enable the internal

LDO output VCC

VENABLE high level

1.2

VEN-VCC-L

Voltage level to disable the internal

LDO output VCC

VENABLE low level

0.4

VEN-VOUT-H

Precision enable level for switching

and regulator output: VOUT

VENABLE high level

2.1

2.42

VEN-VOUT-HYS

Hysteresis voltage between VOUT

precision enable and disable

thresholds

VENABLE hysteresis

–294

ILKG-EN

Enable input leakage current

VEN = 3.3 V

0.8

1.7

µA

INTERNAL LDO (VCC PIN AND BIAS PIN)

VCC

Internal LDO output voltage VCC

VIN ≥ 3.8 V

3.2

VCC-UVLO

Undervoltage lockout (UVLO)

thresholds for VCC

VCC rising threshold

3.15

Hysteresis voltage between rising and

falling thresholds

–575

VBIAS-ON

Internal LDO input change over

threshold to BIAS

VBIAS rising threshold

2.94

3.15

Hysteresis voltage between rising and

falling thresholds

–67

LM46002PWPRG4 Datasheet(PDF) 5 Page - Texas Instruments

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