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LM76005 Datasheet(PDF) 28 Page - Texas Instruments |
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LM76005 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 51 page  Equation 26 yields a value of 315 kΩ. The resulting falling UVLO threshold, can be calculated by Equation 27, where EN falling threshold (VENL) is 0.99 V (typical). VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB (27) 8.2.2.13 PGOOD A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 18 V. If it is desired to pull up the PGOOD pin to a voltage higher than 18 V, a resistor can be added from the PGOOD pin to ground to divide the voltage detected by the PGOOD pin to a value no higher than 18 V. 8.2.2.14 Synchronization The LM76005 switching action can synchronize to an external clock from 200 kHz to 500 kHz. TI recommends connecting an external clock to the SYNC pin with a 50-Ω to 100-Ω termination resistor. Ground the SYNC pin if not used. LM76005 SNVSBK5A – FEBRUARY 2020 – REVISED JULY 2020 www.ti.com 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM76005 |
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