OPA4197IPWR datasheet(31/56 Pages) TI2

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±IN

+IN

V±

V+

OUT

VS+

GND

VS±

GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Use low-ESR, ceramic

bypass capacitor

Place components

close to device and

to each other to

reduce parasitic

errors

VIN

VOUT

(Schematic Representation)

Use low-ESR,

ceramic bypass

capacitor

OPA197, OPA2197, OPA4197

www.ti.com

SBOS737C – JANUARY 2016 – REVISED MARCH 2018

Product Folder Links: OPA197 OPA2197 OPA4197

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10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically

separate digital and analog grounds paying attention to the flow of the ground current. For more detailed

information refer to Circuit Board Layout Techniques, SLOA089.

•

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much

better as opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As shown in Figure 57, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

•

Any precision integrated circuit may experience performance shifts due to moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is

recommended to remove moisture introduced into the device packaging during the cleaning process. A

low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

10.2 Layout Example

Figure 57. Operational Amplifier Board Layout for Noninverting Configuration

OPA4197IPWR Datasheet(PDF) 31 Page - Texas Instruments

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