PCA9535DGVR datasheet(21/51 Pages) TI2

21 / 51 page

The eight registers within the PCA9535 are configured to operate as four register pairs. The four pairs are Input

Ports, Output Ports, Polarity Inversions, and Configurations. After sending data to one register, the next data

byte is sent to the other register in the pair (see Figure 8-8 and Figure 8-9). For example, if the first byte is sent

to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register

may be updated independently of the other registers.

SCL

SDA

Data 0

0.7

0.0

Data 1

1.7

1.0

A2 A1 A0

Slave Address

Command Byte

Data to Port 0

Data to Port 1

Start Condition

Acknowledge

From Slave

Write to Port

Data Out from Port 1

Data Out from Port 0

Data Valid

Acknowledge

From Slave

Acknowledge

From Slave

tpv

R/W

Figure 8-8. Write To Output Port Registers

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SCL

SDA

Data 0

Data to Register

R/W

MSB

LSB

Data 1

MSB

LSB

Data to Register

A2 A1 A0

Acknowledge

From Slave

Acknowledge

From Slave

Start Condition

Command Byte

Slave Address

Acknowledge

From Slave

Figure 8-9. Write To Configuration Registers

8.3.2.4.2 Reads

The bus master first must send the PCA9535 address with the least-significant bit set to a logic 0 (see Figure

8-6 for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the PCA9535 (see Figure 8-10 through Figure

8-12).

After a restart, the value of the register defined by the command byte matches the register being accessed when

the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart

occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original

command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the

the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next

byte read is Input Port 0.

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number

of data bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data

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PCA9535

SCPS129K – AUGUST 2005 – REVISED MARCH 2021

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