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L99PM62GXP Datasheet(PDF) 31 Page - STMicroelectronics

Part # L99PM62GXP
Description  Power management IC with LIN and high speed CAN
PDF  102 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PM62GXP Datasheet(HTML) 31 Page - STMicroelectronics

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L99PM62GXP
Detailed description
Doc ID 17639 Rev 4
31/102
In order to further reduce the current consumption in standby mode, the integrated CAN bus
interface offers an ultra low current consumption.
2.9.1
CAN error handling
The L99PM62GXP provides the following 4 error handling features which are not described
in the ISO 11898-2/ISO 11898-5, but are realized in different stand alone CAN
transceivers/micro controllers to switch the application back to normal operation mode.
At VS > Vpor (i.e. VS power-on reset threshold), the CAN transceiver is enabled. It remains
enabled also in case of VS overvoltage and undervoltage conditions.
The CAN transmitter is disabled only in case of the following errors:
●
Dominant TxDC time out
●
CAN permanent recessive
●
RxDC permanent recessive
●
Thermal shutdown 1
The CAN receiver is not disabled in case of any failure condition.
Dominant TxDC time out
If TXDC is in dominant state (low) for t > tdom(TxD) the transmitter is disabled, status bit is
latched and can be read and optionally cleared by SPI. The transmitter remains disabled
until the status register is cleared.
CAN permanent recessive
If TXDC changes to dominant (low) state but CAN bus does not follow for 4 times, the
transmitter is disabled, status bit is latched and can be read and optionally cleared by SPI.
The transmitter remains disabled until the status register is cleared.
CAN permanent dominant
If the bus state is dominant (low) for t > tCAN a permanent dominant status is detected. The
status bit is latched and can be read and optionally cleared by SPI. The transmitter is not
disabled.
RXDC permanent recessive
If RXDC pin is clamped to recessive (high) state, the controller is not able to recognize a bus
dominant state and could start messages at any time, which results in disturbing the overall
bus communication. Therefore, if RXDC does not follow TXDC for 4 times the transmitter is
disabled. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter remains disabled until the status register is cleared.
2.9.2
Wake up (from CAN)
When the L99PM62GXP is in standby mode with CAN wake up option enabled, the CAN
bus traffic is detected. For the wake up feature the L99PM62GXP logic differentiates
different conditions. During V1 Standby mode RXDC output is kept at recessive level.
Independent from the wakeup pattern selected and independent from the previous Standby
mode, the RXDC reflect immediately the bus state after the wakeup. This feature allows
implementation of a ‘partial networking’ functionality controlled by the system
microcontroller.



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