ETL9444 datasheet(10/27 Pages) STMICROELECTRONICS

10 / 27 page

The 8 L drivers, when enabled, output the contents

of latched Q data to the L I/O ports. Also, the

contents of L may be read directly into A and M. L

I/O ports can be directly connected to the segments

of a multiplexed LED display (using the LED Direct

Drive output configuration option) with Q data being

outputted to the Sa - Sg and decimal point segments

of the display.

The SIO register functions as a 4-bit serial-in/serial-

out shift register or as a binary counter depending

on the contents of the EN register. (See EN register

description, below). Its contents can be exchanged

with A, allowing it to input or output a continuous se-

rial data stream, SIO may also be used to provide

additional parallel I/O by connecting SO to external

serial-in/parallel-out shift registers.

The XAS instruction copies C into the SKL latch. In

the counter mode, SK is the output of SKL ; in the

shift register mode, SK outputs SKL ANDed with the

clock.

The EN register is an internal 4-bit register loaded

under program control by the LEI instruction. The

state of each bit of this register selects or deselects

the particular feature associated with each bit of the

EN register (EN3-EN0).

1. The least significant bit of the enable register,

EN0, selects the SIO register as either a4-bit shift

SIO is an asynchronous binary counter, decre-

menting its value by one upon each low-going

pulse (”1” to ”0”) ocurring on the SI input. Each

pulse must be at least two instruction cycles

wide. SK outputs the value of SKL. The SO out-

put is equal to the value of EN3. With EN0 reset,

SIO is a serial shift register shifting left each in-

struction cycle time. The data present at SI goes

into the least significant bit of SIO. SO can be en-

abled to output the most significant bit of SIO

each cycle time. (See 4 below). The SK output

becomes a logic-controlled clock.

2. With EN1 set the IN1 input is enabled as an in-

terrupt input. Immediately following an interrupt,

EN1 is reset to disable further interrupts.

3. With EN2 set, the L drivers are enabled to output

the data in Q to the L I/O ports. Resetting EN2 di-

sables the L drivers, placing the L I/O ports in a

high-impedance input state.

4. EN3, in conjunction with EN0, affects the SO out-

put. With EN0 set (binary counter option selec-

ted) SO will output the value loaded into EN3.

With EN0 reset (serial shift register option selec-

ted), setting EN3 enables SO as the output of the

SIO shift register, outputting serial shifted data

each instruction time. Resetting EN3 with the se-

rial shift register option selected disables SO as

the shift register output ; data continues to be

shifted through SIO and can be exchanged with

A via an XAS instruction but SO remains reset to

”0”. The table below provides a summary of the

modes associated with EN3 and EN0.

Enable Register Modes - Bits EN3 and EN 0

EN 3

EN 0

SI O

S I

S O

Shift Register

Binary Counter

Input to Shift Register

Input to Binary Counter

Serial Out

If SKL = 1, SK = Clock

If SKL = 0, SK = 0

If SKL = 1, SK = Clock

If SKL = 0, SK = 0

If SKL = 1, SK = 1

If SKL = 0, SK = 0

If SKL = 1, SK = 1

If SKL = 0, SK = 0

INTERRUPT

The following features are associated with the IN1

interrupt procedure and protocol and must be consi-

dered by the programmer when utilizing interrupts.

a. The interrupt, once acknowledged as explained

below, pushes the next sequential program

counter address (PC + 1) onto the stack, pushing

in turn the contents of the other subroutine-save

registers to the next lower level

(PC + 1

→ SA → SB → SC). Any previous

contents of SC are lost. The program counter is

set to hex address 0FF (the last word of page 3)

and EN1 is reset.

b. An interrupt will be acknowledged only after the

following conditions are met :

1. EN1 has been set.

2. A low-going pulse (”1” to ”0”) at least two in-

struction cycles wide occurs on the IN1 input.

3. A currently executing instruction has been

completed.

ETL9444/9445–ETL9344/9345

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