INPUT/OUTPUT INSTRUCTIONS

Mnem Operand

Hex

Code

Machine

Language

Code

(binary)

Data Fl ow

Skip

Conditions

Description

ING

33

2A

| 0 0 11| 0 011 |

_______________

| 0 0 10| 1 010 |

_______________

G

→ A

None

Input G Ports to A

ININ

33

28

| 0 0 11| 0 011 |

_______________

| 0 0 10| 1 000 |

_______________

IN

→ A

None

Input IN Inputs to A

(note 2)

INIL

33

29

| 0 0 11| 0 011 |

_______________

| 0 0 10| 1 001 |

_______________

None

Input IL Latches to A

(note 3)

INL

33

2E

| 0 0 11| 0 011 |

_______________

| 0 0 10| 1 110 |

_______________

→ RAM(B)

None

Input L Ports to RAM, A

OBD

33

3E

| 0 0 11| 0 011 |

_______________

| 0 0 11| 1 110 |

_______________

Bd

→ D

None

Output Bd to D Outputs

OGI

y

33

5–

| 0 0 11| 0 011 |

_______________

| 0 1 01|

y

|

_______________

y

→ G

None

Output to G Ports

Immediate

OMG

33

3A

| 0 0 11| 0 011 |

_______________

| 0 0 11| 1 010 |

_______________

RAM(B)

→ G

None

Output RAM to G Ports

XAS

4F

| 01 00| 1 111 |

_______________

A £ SIO, C

→ SKL

None

Exchange A with SIO

(note 3)

Notes :

1.All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are

(left-most) bit of the 4-bit A register.

2.The ININ instruction is not available on the 24-pin ETL9445 or ETL9345 since these devices do not contain the IN inputs.

3.For additional information on the operation of the XAS, JID, LQUID, INIL and SKT instructions, see below.

4.The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or

3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word

of a page.

5.A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in

pages 2 or 3, JSRP may not jump to the last word in page 2.

6.LBI is a single-byte instruction if d = 0, 9, 10, 11, 12, 13, 14 or 15. The machine code for the lower 4 bits equals the binary value of

7.Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ”1” or ”0” in each bit

of EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN

Register).

The following information is provided to assist the u-

ser in understanding the operation of several unique

instructions and to provide notes useful to program-

mers in writing ETL9444/L9445 programs.

XAS INSTRUCTION

XAS (Exchange A with SIO) exchanges the 4-bit

contents of the accumulator with the 4-bit contents

of the SIO register. The contents of SIO will contain

serial-in/serial-out shift register or binary counter da-

ta, depending on the value of the EN register. An

XAS instruction will also affect the SK output. (See

Functional Description, EN Register, above). If SIO

is selected as a shift register, an XAS instruction

must be performed once every 4 instruction cycles

to effect a continuous data stream.

JID INSTRUCTION

JID (Jump Indirect) is an indirect addressing instruc-

tion, transferring program control to a new ROM lo-

cation pointed to indirectly by A and M. It loads the

lower 8 bits of the ROM address register PC with the

contents of ROM addressed by the 11-bit word,

this instruction.

Note that JID requires 2 instruction cycles to exe-

cute.

INIL INSTRUCTION

latches are set if a low-going pulse (”1” to ”0”) has

ETL9444/9445–ETL9344/9345

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