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SN74ACT86DBR Datasheet(PDF) 9 Page - Texas Instruments |
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SN74ACT86DBR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 38 page ![]() 7 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 7.1 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in Figure 7-1. 7.2 Layout 7.2.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 7.2.2 Layout Example 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 2A 2B 2Y GND V CC 4B 4A 3B 3A 3Y GND V CC 4Y 1Y 0.1 F Unused inputs tied to VCC Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Figure 7-1. Example Layout for the SN74ACT86 www.ti.com SN54ACT86, SN74ACT86 SCAS534E – AUGUST 1995 – REVISED APRIL 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN54ACT86 SN74ACT86 |
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