SN74LVC74APWR datasheet(12/46 Pages) TI2

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• Load currents must not exceed (IO max) per output and must not exceed (Continuous current through

VCC or GND) total current for the part. These limits are located in Absolute Maximum Ratings.

• Outputs must not be pulled above VCC.

8.2.3 Application Curves

VOL – V

–20

100

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

TA = 25°C, VCC = 3 V,

VIH = 3 V, VIL = 0 V,

All Outputs Switching

Figure 8-2. Output Drive Current (IOL)

vs LOW-level Output Voltage (VOL)

–100

–80

–60

–40

–20

–1

–0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

TA = 25°C, VCC = 3 V,

VIH = 3 V, VIL = 0 V,

All Outputs Switching

VOH – V

Figure 8-3. Output Drive Current (IOH)

vs HIGH-level Output Voltage (VOH)

8.3 Power Supply Recommendations

The power supply may be any voltage between the minimum and maximum supply voltage rating located in

Recommended Operating Conditions .

Each VCC terminal must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is

recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01-µF or 0.022-µF

capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to

reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies

of noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results.

8.4 Layout

8.4.1 Layout Guidelines

Inputs must not float when using multiple bit logic devices. In many cases, functions or parts of functions of

digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND

gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected

because the undefined voltages at the outside connections result in undefined operational states.

Specified in Figure 8-4 are rules that must be observed under all circumstances. All unused inputs of digital logic

devices must be connected to a high or low bias to prevent them from floating. The logic level that must be

applied to any particular unused input depends on the function of the device. Generally, they are tied to GND or

VCC, whichever makes more sense or is more convenient.

SN54LVC74A, SN74LVC74A

SCAS287W – JANUARY 1993 – REVISED DECEMBER 2024

www.ti.com

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