IN

EN1

EN2

GND

OUT1

OUT2

ON

OFF ON

OFF

V

IN

C

IN

(1)

C

1 F

Ceramic

m

OUT1

(1)

C

1 F

Ceramic

m

OUT2

(1)

V

OUT1

V

OUT2

TLV716, TLV716P

SBVS217B – JUNE 2013 – REVISED NOVEMBER 2015

www.ti.com

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLV716 and TLV716P belong to a family of dual-channel, capacitor-free, 150-mA, low-dropout voltage

(LDO) regulators. These devices can be used with or without external capacitors and are available in a 1.2-mm ×

1.2-mm package, making these devices a very small solution size for dual-channel, low-dropout (LDO)

regulators. This family of LDO regulators offers current limit and thermal protection, and is specified from –40°C

to 85°C. Figure 24 shows an application circuit for this family of devices.

8.2 Typical Application

(1)

Optional.

Figure 24. Typical Application Circuit

8.2.1 Design Requirements

Table 1 lists the design requirements.

Table 1. Design Parameters

PARAMETER

DESIGN REQUIREMENT

Input voltage

4.2 V to 3 V (Lithium Ion battery)

Output 1 voltage

2.8 V ±1.5%

Output 1 DC current

50 mA

Output 2 voltage

1.8 V ±1.5%

Output2 DC current

10 mA

Maximum ambient temperature

65°C

8.2.2 Detailed Design Procedure

An input capacitor is not required for this design because of the low impedance connection directly to the battery.

No output capacitor allows for the minimal possible inrush current during start-up, ensuring the 180-mA

maximum input current limit is not exceeded. Verify that the maximum junction temperature is not exceeded by

calculating the total power dissipation and the junction temperature rise. For this example the total worst case

power dissipation is (4.2 V - 2.8 V) × 0.05 A + (4.2 V - 1.8 V) × 0.01 = 0.094 W. The rise in junction temperature

is calculated by multiplying the power dissipation by thermal resistance RθJA. For this example, assuming the

board size is similar to the JEDEC High K standard, the rise in junction temperature is 0.094 W × 149.3 °C/W =

14°C. The junction temperature is calculated by adding the rise in junction temperature to the maximum ambient

temperature; in this example the maximum junction temperature can be calculated to be 65°C + 14°C = 79°C. It

is mandatary to keep the junction temperature below the maximum operating junction temperature. For additional

thermal information see the Thermal Considerations and Power Dissipation sections.

12

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