XIO2001IPNP datasheet(103/145 Pages) TI2

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8.6.3 GPIO Control Register

This register controls the direction of the five GPIO terminals. This register has no effect on the behavior of GPIO

terminals that are enabled to perform secondary functions. The secondary functions share GPIO0 (CLKRUN),

GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL). This register is an alias of the GPIO control register in

the classic PCI configuration space(offset B4h, see Section 8.4.60). See Table 8-75 for a complete description of

the register contents.

Device control memory window register offset:

40h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 8-75. GPIO Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:5

RSVD

Reserved. Returns 0000 0000 000b when read.

4(1)

GPIO4_DIR

GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.

0 = Input (default)

1 = Output

3(1)

GPIO3_DIR

GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.

0 = Input (default)

1 = Output

2(1)

GPIO2_DIR

GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.

0 = Input (default)

1 = Output

1(1)

GPIO1_DIR

GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.

0 = Input (default)

1 = Output

0(1)

GPIO0_DIR

GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.

0 = Input (default)

1 = Output

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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