XIO2001IPNP datasheet(105/145 Pages) TI2

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8.6.6 Serial-Bus Word Address Register

The value written to the serial-bus word address register represents the word address of the byte being read

from or written to on the serial-bus interface. The word address is loaded into this register prior to writing the

serial-bus slave address register that initiates the bus cycle. This register is an alias for the serial-bus word

address register in the PCI header (offset B1h, see Section 8.4.57). This register is reset by a PCI Express reset

( PERST), a GRST, or the internally-generated power-on reset.

Device control memory window register offset:

45h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

8.6.7 Serial-Bus Slave Address Register

The serial-bus slave address register indicates the address of the device being targeted by the serial-bus cycle.

This register also indicates if the cycle will be a read or a write cycle. Writing to this register initiates the cycle on

the serial interface. This register is an alias for the serial-bus slave address register in the PCI header (offset

B2h, see Section 8.4.58). See Table 8-77 for a complete description of the register contents.

Device control memory window register offset:

46h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 8-77. Serial-Bus Slave Address Register Descriptions

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:1(1)

SLAVE_ADDR

Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

transaction. The default value for this field is 000 0000b.

0(1)

RW_CMD

Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

0 = A single byte write is requested (default)

1 = A single byte read is requested

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.6.8 Serial-Bus Control and Status Register

The serial-bus control and status register controls the behavior of the serial-bus interface. This register also

provides status information about the state of the serial-bus. This register is an alias for the serial-bus control

and status register in the PCI header (offset B3h, see Section 8.4.59). See Table 8-78 for a complete description

of the register contents.

Device control memory window register offset:

47h

Read-only, Read/Write, Read/Clear

Default value:

00h

BIT NUMBER

RESET STATE

Table 8-78. Serial-Bus Control and Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

PROT_SEL

Protocol select. This bit selects the serial-bus address mode used.

0 = Slave address and word address are sent on the serial-bus (default)

1 = Only the slave address is sent on the serial-bus

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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