TLV702xx

GND

EN

IN

OUT

V

IN

V

OUT

On

Off

C

IN

C

OUT

1

F

Ceramic

m

13

TLV702

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SLVSAG6D – SEPTEMBER 2010 – REVISED JULY 2019

Product Folder Links: TLV702

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLV702 belongs to a new family of next-generation value LDO regulators. These devices consume low

quiescent current and deliver excellent line and load transient performance. These characteristics, combined with

low noise and very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for portable

RF applications. This family of regulators offers current limit and thermal protection, and is specified from –40°C

to +125°C.

8.2 Typical Application

Figure 25. Typical Application Circuit

8.2.1 Design Requirements

Table 2 lists the design parameters.

Table 2. Design Parameters

PARAMETER

DESIGN REQUIREMENT

Input voltage

2.5 V to 3.3 V

Output voltage

1.8 V

Output current

100 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

1-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation

in value and equivalent series resistance (ESR) overtemperature.

However, the TLV702 is designed to be stable with an effective capacitance of 0.1 μF or larger at the output.

Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance

under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the

capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance

after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of

lower-cost dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use of

smaller footprint capacitors that have higher derating in size- and space-constrained applications.

Using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective

capacitance under the specified operating conditions must not be less than 0.1 μF. Maximum ESR should be

less than 200 mΩ.