TLV2372IP datasheet(28/66 Pages) TI2

28 / 66 page

55 -40 -25 -10

95 110 125

Temperature ( C)

1.75

1.5

1.25

0.75

0.5

0.25

SOT-23 Package

Low-K Test PCB

= 324

C/W

SOIC Package

Low-K Test PCB

= 176

C/W

PDIP Package

Low-K Test PCB

= 104

C/W

MSOP Package

Low-K Test PCB

= 260

C/W

T = 150 C

MAX

N/C

–IN

+IN

V–

N/C

V+

OUTPUT

N/C

Use low-ESR, ceramic

bypass capacitor

GND

VS+

Run the input traces

as far away from

the supply lines

as possible

Place components

close to device and

to eachother to

reduce parasitic

errors

GND

VIN

GND

Use low-ESR,

ceramic bypass

capacitor

VS–

VOUT

TLV2370, TLV2371, TLV2372

TLV2373, TLV2374, TLV2375

SLOS270F – MARCH 2001 – REVISED AUGUST 2016

www.ti.com

Product Folder Links: TLV2370 TLV2371 TLV2372 TLV2373 TLV2374 TLV2375

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Layout Example (continued)

Figure 41. Operational Amplifier Board Layout for Noninverting Configuration

11.3 Power Dissipation Considerations

For a given θJA, the maximum power dissipation is shown in Figure 42 and is calculated by Equation 4:

where

•

PD = Maximum power dissipation of TLV237x IC (watts)

•

TMAX = Absolute maximum junction temperature (150°C)

•

TA = Free-ambient air temperature (°C)

•

θJA = θJC (Thermal coefficient from junction to case) + θCA (Thermal coefficient from case to ambient air (°C/W))

(4)

Results are with no air flow and using JEDEC Standard Low-K test PCB.

Figure 42. Maximum Power Dissipation vs Free-Air Temperature

TLV2372IP Datasheet(PDF) 28 Page - Texas Instruments

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