RT7296F

Copyright © 2023 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

DS7296F-06

September

2023

www.richtek.com

3

Functional Block Diagram

EN/SYNC

+

-

UV

Comparator

Oscillator

0.4V

Internal

Regulator

Shutdown

Comparator

BOOT

VIN

GND

SW

FB

HS Switch

Current

Comparator

+

-

EA

0.807V

Power

Stage &

Deadtime

Control

+

-

1.4V

+

Slope

Compensation

LS Switch

Current

Comparator

UVLO

Logic &

Protection

Control

BOOT

UVLO

Current

Sense

Current

Sense

PVCC

Internal SS

PG

50pF

1pF

400k

Operation

Power Saving Mode

The RT7296F automatically enters into power saving

mode (PSM) at light load to improve efficiency. In PSM,

the RT7296F disable the internal CLK when VFB is

above the VREF x 1.005 (typ.). In other words, the

device automatically skip the PWM pulse at light load.

While VFB falls below the VREF x 1.005, the RT7296F

enables the internal CLK again and hence the new

switching cycle is activated. When the internal switches

are activated, for each cycle the device detects the

peak inductor current (IL_PEAK) and keeps high-side

switch on until the IL reaches its minimum peak current

level (as shown in Figure 1). When low-side switch is

turn-on, the zero-current detection is also activated to

prevent that IL becomes negative and enables the

higher efficiency at light load. During the period that

both switches are off, the device turns off the most of

the internal circuit to reduce the quiescent power

consumption further.

With lower output loading, the non-switching period is

longer, so the effective switching frequency becomes

lower to reduce the switching loss and switch driving

loss.

IL

SW

MPC

Figure 1. Minimum Peak Current at PSM

Power Good Indication

The RT7296F features an open-drain power-good

output (PG) to monitor the output voltage status.

Connect PG to PVCC or an external voltage below

5.5V with a resistor. The power-good function is

activated after soft-start is finished and is controlled by

a comparator connected to the feedback signal VFB. If

VFB rises above a power-good high threshold (PGvth_Hi,

typically 90% of the reference voltage), the PG pin will

be in high impedance and VPG will be held high after a

certain delay elapsed (typically, 400

s). When VFB fall

short of power good low threshold (PGvth_Lo, typically

85% of the reference voltage), the PG pin will be pulled

low.