9.3 Power Supply Recommendations

The device is designed to operate from a VBIAS range of 2.5 V to 5.7 V and a VIN range of 0.6 V to VBIAS.

9.4 Layout

9.4.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output

capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have

on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects

along with minimizing the case to ambient thermal impedance.

9.4.2 Layout Example

Notice the thermal vias located under the exposed thermal pad of the device. This allows for thermal diffusion

away from the device.

CT1 capacitor

CT2 capacitor

VIN1 capacitor

VOUT1 capacitor

VIN2 capacitor

VOUT2 capacitor

Thermal

relief vias

Figure 9-8. PCB Layout Example

9.4.3 Power Dissipation

The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To

calculate the maximum allowable power dissipation, PD(max) for a given output current and ambient temperature,

use Equation 6.

J(max)

A

D(max)

JA

T

T

P

-

=

θ

(6)

where

• PD(max) is the maximum allowable power dissipation.

• TJ(max) is the maximum allowable junction temperature (125°C for the TPS22976).

• TA is the ambient temperature of the device.

• θJA is the junction to air thermal impedance. See the Thermal Information section. This parameter is highly

dependent upon board layout.

www.ti.com

TPS22976

SLVSDE7D – NOVEMBER 2016 – REVISED DECEMBER 2023

Copyright © 2023 Texas Instruments Incorporated

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Product Folder Links: TPS22976