Copyright © 2016

Microsemi

Page 23

Rev. 1.4, July 2017

CPG

– PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70211

PD Controller with Switching Regulator for

AF/AT/UPOE/HDBaseT/4-pair PoE Applications

Setting the Voltage Divider for Output Rails

Generically, we can state the equation to be



 UP

LOW

OUT

X

LOW

RR

VV

R

Where RUP is the name we have given to the upper resistor (connected to output rail) and RLOW is the name we

have given here to the resistor connected to lower rail (usually IC ground). However, there are so many

topologies, we have in effect thress cases in all the typical schematics presented so far.

a) Non-isolated topologies with simple divider connected directly to FB pin. For this use VX = 1.2V.

b) Isolated topologies with divider to another reference (such as TL431 with an internal reference of 2.5V).

For this use VX = 2.5V.

c) Non-isolated topologies with a differential divider connected to differential voltage amplifier of the

LX7309 . Here we use the same divider equation provided above, but using VX = 0.171V (that is 1.2V

divided down by the gain of the diff-amp, i.e. by 7). We need two identical dividers.

Selecting the Sense Resistor

In a Buck topology, the center of the switch current ramp equals the output current. To that we need to add

about 30% for the peak current “IPEAK+” because of the rising ramp caused by the inductor. That is a factor of 1.3.

We also need to include some headroom for proper transient response at max load. Since the peak voltage on

the sense resistor is 0.2V, to leave headroom, we should plan that the switch current peak stays at around 0.18V

max at max load. This means that:







PEAK

O

SENSE

OO

I

1.3 I , So

0.18

0.138

R

=

1.3 I

I

SENSE

O

0.138

R

=

(Buck)

I

Assuming we have designed the converter to operate up to 44% max duty cycle, we can quickly estimate the

peak current as follows.