www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

(3.3)

(3.3)

14X (0.6)

14X (0.24)

8X (0.5)

(R0.05) TYP

(

0.2) TYP

VIA

(2.05)

(2.05)

(0.845)

(0.845)

(1.5)

(0.55)

4X (0.2)

2X (0.525)

4X

(R0.12)

VQFN - 1 mm max height

RHL0014A

PLASTIC QUAD FLATPACK - NO LEAD

4228405/A 01/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

SYMM

SYMM

METAL UNDER

SOLDER MASK

SOLDER MASK OPENING

1

2

6

7

8

9

13

14

15

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

DEFINED