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STM32F101V8 Datasheet(PDF) 97 Page - STMicroelectronics

Part # STM32F101V8
Description  Medium-density access line, ARM®-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces
PDF  101 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101V8 Datasheet(HTML) 97 Page - STMicroelectronics

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DocID13586 Rev 17
97/101
STM32F101x8, STM32F101xB
Revision history
100
14-Mar-2008
5
Figure 2: Clock tree on page 13 added.
CRC added (see CRC (cyclic redundancy check) calculation unit on
page 9 and Figure 8: Memory map on page 29 for address).
Maximum TJ value given in Table 7: Thermal characteristics on page 33.
PD, TA and TJ added, tprog values modified and tprog description clarified in
Table 27: Flash memory characteristics on page 51.
IDD modified in Table 15: Typical and maximum current consumptions in
Stop and Standby modes on page 39.
ACCHSI modified in Table 23: HSI oscillator characteristics on page 49,
note 2 removed.
tRET modified in Table 27: Flash memory characteristics.
VNF(NRST) unit corrected in Table 36: NRST pin characteristics on
page 60.
Table 40: SPI characteristics on page 65 modified.
IVREF added in Table 41: ADC characteristics on page 68.
Table 43: ADC accuracy - limited test conditions added. Table 44: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 73).
Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints
added (see Figure 44, Figure 47, Figure 50 and Figure 41).
Section 6.7: Thermal characteristics on page 90 modified.
Appendix A: Important notes removed.
21-Mar-2008
6
Small text changes.
In Table 27: Flash memory characteristics:
–NEND tested over the whole temperature range
– cycling conditions specified for tRET
–tRET min modified at TA = 55 °C
Figure 2: Clock tree corrected. Figure 8: Memory map clarified.
V25, Avg_Slope and TL modified in Table 45: TS characteristics.
CRC feature removed.
22-May-2008
7
Section 1: Introduction modified, Section 2.2: Full compatibility throughout
the family added. CRC feature added.
IDD_VBAT removed from Table 21: Typical current consumption in Standby
mode on page 42.
Values added to Table 39: SCL frequency (fPCLK1= 36 MHz, VDD_I2C =
3.3 V) on page 64.
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 66
modified. Equation 1 corrected.
Section 6.7.2: Evaluating the maximum junction temperature for an
application on page 91 added.
Axx option added to Table 52: Ordering information scheme on page 92.
Table 53. Document revision history (continued)
Date
Revision
Changes



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