DAC38RF86 datasheet(20/147 Pages) TI2

Part #	DAC38RF86

Description	DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL

PDF	147 Pages

Scroll/Zoom	100%

Manufacturer	TI2 [Texas Instruments]

Direct Link	https://www.ti.com

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20 / 147 page

DAC38RF86, DAC38RF96

DAC38RF87, DAC38RF97

SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017

www.ti.com

Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97

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7.9 Timing Requirements

MIN

NOM

MAX

UNIT

DIGITAL INPUT TIMING SPECIFICATIONS

TIMING: SYSREF+/-

ts(SYSREF)

Setup time, SYSREF+/- valid to rising

edge of DACCLK+/-

SYSREF Capture assist disabled

th(SYSREF)

Hold time, SYSREF+/- valid after rising

edge of DACCLK+/-

SYSREF Capture assist disabled

TIMING: SERIAL PORT

ts(/SDEN)

Setup time, SDEN to rising edge of SCLK

ts(SDIO)

Setup time, SDIO valid to rising edge of SCLK

th(SDIO)

Hold time, SDIO valid after rising edge of SCLK

t(SCLK)

Period of SCLK

temperature sensor read

µs

All other registers

100

td(Data)

Data output delay after falling edge of SCLK

tRESET

Minimum RESET pulse width

ANALOG OUTPUT

ts(DAC)

Output settling time to 0.1%

Output rise time 10% to 90%

Output fall time 90% to 10%

LATENCY

RX SerDes AnalogDelay

250

DAC wake-up time

IOUT current settling to 1% of IOUTFS

from deep sleep

µs

DAC sleep time

IOUT current settling to less than 1% of

IOUTFS in deep sleep

µs

DAC38RF86 Datasheet(PDF) 20 Page - Texas Instruments

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